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Install Verilator from or use apt-get install verilator. To prepare the simulation, the following steps (tested on Ubuntu and Debian hosts) can be followed: The PulseRain Reindeer can be simulated with Verialtor. *) The Microsemi FPGA bitstream for Future Electronics Creative board (SmartFusion2) can be found in *) The Lattice FPGA bitstream for Gnarly Grey UPDuinoV2 board can be found in (In the repository, the Reindeer.vm has already been imported and put in. Use synplify_pro (part of Microsemi Libero SoC V11.9) to open, and generate Reindeer.vmД¬lose synplify_pro and use Libero SoC V11.9 to open, import the Reindeer.vm produced in the previous step, and start the build process to generate bitstream. To build bistream for Future Electronics Creative board (SmartFusion2), do the following:

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To build bitstream for Gnarly Grey UPDuinoV2 board, use Lattice Radiant 1.0.1 software to open Synthesis related constraint files can be found in, and PAR related constraint files can be found in.

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And the platform independent verilog code can be found in Д¬onstraint and other FPGA-related files necessary to produce a binary bitstream for the respective hardware The platform dependent top level verilog code can be found in. The folder structure of the GitHub repository is illustrated below:ДЄnd here is a brief index of the key items in the repository: If Flash is used to store the software image, the OCD can be modified a little bit to read from the flash instead of the external host.

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This makes it more portable across all FPGA platforms. At that point, the OCD can switch the UART TX back to the CPU side for CPU's output.ДЄs the hold-and-load gets software images from an external host, it does not need any ROM to begin with. A new software image can be loaded into the memory during the CPU hold state, which gives rise to the name 'hold-and-load'.ДЄfter the memory is loaded with the new image, the OCD can setup the start-address of the soft CPU, and send start pulse to make the soft CPU active.

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But a valid debug frame sending from the host PC can let OCD to reconfigure the mux and switch the UART TX to OCD side, for which the memory can be accessed, and the control frames can be exchanged.

And that mux is controlled by the OCD.ДЄfter reset, the soft CPU will be put into a hold state, and it will have access to the UART TX port by default. The RX signal goes to both the soft CPU and OCD, while the TX signal has to go through a mux. The soft CPU and the OCD can share the same UART port, as illustrated above. To break the status quo, the PulseRain Reindeer takes a different approach called 'hold and load', which brings a hardware based OCD (on-chip debugger) into the fore, as illustrated below: In other words, the soft CPU might have to improvise a little bit to work on various platforms. And when it comes to SoC + FPGA, like the Microsemi Smartfusion2, a hardcore processor could also be involved in the boot-loading. The boot loader itself could be executed in place, or loaded with a small preloader implemented in FPGA fabric. For some FPGAs, like Intel Cyclone or Xilinx Artix, the memory initial data can be stored in FPGA bitstream, but other platforms might choose to use external flash for the ROM data.

The implementation of ROM is not consistent across all FPGA platforms.

The bootloader will be more or less intrusive, as it takes memory spaces.

And the PC will be set to the _start address of the new image afterwards.

After power on reset, the boot loader is supposed to be executed first, for which it will move the rest of the code/data into RAM.

The traditional approach is more or less like the following: Highlights - Hold and LoadД«ootstrapping a soft CPU tends to be a headache. And those platforms will find themselves a good match with the PulseRain Reindeer when it comes to soft CPU. Some FPGA platforms, like the Lattice iCE40 UltraPlus family, carry a large amount of SPRAM with very little EBR RAM. Thanks to using single port memory to store both code and data, the Reindeer soft CPU is quite portable and flexible across all FPGA platforms. In this way, the Instruction Fetch and Memory Access always happen on different clock cycles, thus to avoid the structural hazard caused by the single port memory. For the even cycle, only IF and IE stages are active, while for the odd cycle, only ID and MEM stages are active. In the 2 x 2 layout, each stage is active every other clock cycle. However, unlike traditional pipelines, Reindeer's pipeline stages are mapped to a 2 x 2 layout, as illustrated below:

Reindeer's pipeline is composed of 4 stages: It strives to make a balance between speed and area, and offers a flexible choice for soft CPU across all FPGA platforms. It supports RISC-V RV32I instruction set, and features a 2 x 2 pipeline. PulseRain Reindeer is a soft CPU of Von Neumann architecture.

PulseRain Reindeer - RISCV RV32I Soft CPU

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